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Add Phase 0 host-bridge: relay text across Meshtastic, MeshCore, Reticulum

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archipelago
2026-06-30 20:32:38 -04:00
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README.md
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@@ -13,13 +13,19 @@ the `archy` (Archipelago) codebase. This repo is intentionally standalone.
## Status
Pre-design. See `docs/ARCHITECTURE.md` (in progress) for the protocol
research and bridge design space.
Architecture phase done — see `docs/ARCHITECTURE.md` for the protocol
research, hardware constraints (target: Heltec WiFi LoRa 32 V3), and
phased plan. **Phase 0** (host-side bridge across 3 separate stock-firmware
boards) is written — see `host-bridge/` — but not yet hardware-tested; no
LoRa boards have been attached to the dev machine this was written on.
## Layout
- `docs/` — protocol research notes and architecture/design docs
- `firmware/` — device firmware (once design lands)
- `host-bridge/` — Phase 0: Python bridge relaying text between real
Meshtastic/MeshCore/RNode-Reticulum boards over each project's official
client protocol
- `firmware/` — Phase 1+ embedded firmware (once Phase 0 is validated on hardware)
- `hardware/` — reference hardware notes / board selection
## Non-goals (for now)